Flip chip packages are becoming more popular as they offer several advantages over traditional wire-bonded packages. These advantages include compactness, ruggedness, and cost. The surface of an advanced flip chip is typically provided with solder balls and a passivation layer. The passivation layer material may be silicon nitride, a polyimide, a photosensitive polyimide or a benzocyclobutane polymer. The solder balls comprise a lead (Pb) and tin (Sn) alloy or a Pb-free alloy, whereby the major metallic component of the latter is Sn. As Pb is an undesirable pollutant, current chips tend to use Pb-free solder balls for bonding to protect the environment. In the process of producing the Pb-free solder balls, the surface of a polymer passivation layer, which is provided, often includes organic, inorganic and/or metallic contaminants.
FIG. 1(a) and FIG. 1(b) show the schematic cross-sections of flip chip plastic ball grid array (FC-PBGA) packages that are built partially and completely, respectively. In a typical manufacturing process of FC-PBGA package 10, as shown in FIG. 1(b), chip 12 with solder balls is placed over and electrically connected to laminate 16 in which electrical contacts of chip 12 on a dielectric surface 15 are electrically connected to circuitry of laminate substrate 16 preferably by a heating cycle to form solder interconnections 14 which may be in the form of solder joints. When the chip 12 is electrically connected to the laminate 16, flux is used to join the flip chip to the laminate through melting of the solder balls. Flux is made of solvents and active ingredients such as organic acids that promote metal to metal bonding. Typical fluxes that are used are classified either as water-soluble or as no-clean fluxes. The subsequently formed flux residue on the surfaces of the chip and the laminate needs to be cleaned since the residue often causes underfill-chip delamination. This cleaning process is called “post chip join cleaning”. In the water-soluble fluxes, a post chip join cleaning process comprises applying warm deionized (DI) water into a gap between chip 12 and laminate 16 of a partially manufactured flip chip package 11 in FIG. 1(a). However, contaminants on the chip passivation layer surface, which are introduced in the manufacturing process of the chip, render the post chip joining cleaning process difficult to implement since a certain level of the residue remains in an uncleaned condition.
The dielectric surfaces of the chip and the laminate are treated with oxygen plasma to activate the dielectric surface 15 as well as the laminate surface. As shown in FIG. 1(b), underfill 17 is applied into the gap between the connected contacts of chip 12 and laminate substrate 16. The underfill material is an electrically nonconductive coupling material. The underfill material 17 acts as a buffer for stresses that arise due to the difference between the coefficient of thermal expansion (CTE) of the chip and the laminate substrate as well as due to thermal expansion of solder joints. The underfill material also serves to protect the soldered connections 14 from moisture and may extend past the periphery (or, edge) 20 of chip 12.
However, the underfill-chip interface evidences a tendency to delaminate in the presence of a certain level of residue on the chip passivation layer surface. In that instance, the delamination frequently leads to an extrusion of solder so as to form a tin bridge 27 between adjacent solder joints 14, thereby resulting in electrical shorts. FIGS. 2, 3, and 4(a) illustrate the effects of unremoved residue of a wafer arrangement of a wafer and bonded solder joints. FIGS. 2(a) and 2(b) show the microscope pictures of the chip side of a package that has electrical shorts. FIG. 2(b) shows extruded solder 27 between two solder joints 14 (C4 joints) on the chip surface. FIG. 3(a) shows an example of an X-ray Photoelectron Spectroscopy (XPS) spectrum of an incoming chip that shows a presence of fluorine F1s (1s orbital), oxygen O1s (1s orbital), nitrogen N1s (1s orbital), and carbon C1s (1s orbital). FIG. 3(b) shows a high resolution C1s (carbon) XPS that indicates a typical graphitic layer formation on polyimide. Both the graphitic and the fluorinated layers not only cause underfill-chip delamination but also make the post chip join cleaning difficult so that flux residues are left uncleaned. Upon reflow, tin solder extruded into the small gap between two solder joints to form a bridge of conductive material to produce an electrical short. FIG. 4(a) is an XPS spectrum of the polyimide surface of an electronics chip package cleaned according to prior art methods.
The contaminants on the passivation layer surface of a chip often include organic, inorganic and/or organometallic materials, which are fluorinated and graphitic layers, calcium sulfate (CaSO4) particles, tin oxides, and organotin, respectively. The graphitic and fluorinated layers can be easily removed with a typical O2 gas plasma but the inorganic and organometallic reside cannot be removed with O2 plasma. There is a need to remove or reduce the level of contaminants with a new process to achieve a clean polymer passivation layer surface to provide a reliable FC-PBGA package.